This invention relates to a DMA (direct memory access) request controlling arrangement for use in a DMA controller.
As is known in the art, a DMA controller controls direct transfer of data between a peripheral device and a memory in synchronism with a sequence of clock pulses of a common clock pulse period. The peripheral device comprises a DMA request signal producer for producing a DMA request signal. The DMA request signal has request and nonrequest levels which represent generation and nongeneration of a DMA request, respectively. Such a DMA controller is disclosed in, for example, Microprocessor and Peripheral Handbook, Volume I-Microprocessor, Intel manual (INTEL Corp., Santa Clara, Calif.), pages 2-222 to 2-240 (October, 1987), under the heading of "8237A HIGH PERFORMANCE PROGRAMMABLE DMA CONTROLLER".
The DMA request controlling arrangement controls the DMA request signal to produce a DMA acknowledgement signal and to deliver the DMA acknowledgement signal to the peripheral device. The DMA acknowledgement signal has acknowledged and nonacknowledged levels which represent generation and nongeneration of a DMA acknowledgement signal for the DMA request, respectively. The DMA acknowledgement signal of the acknowledged level initiates the transfer of data between the peripheral device and the memory. In order for the peripheral device to start the direct transfer of data, the DMA request signal must be kept at the request level in the peripheral device until the DMA acknowledgement signal achieves the acknowledged level.
The peripheral device carries out the direct transfer of data in a demand transfer mode. In the demand transfer mode, the peripheral device successively carries out the direct transfer of data to the memory. The peripheral device maintains the DMA request signal continuously at the request level until the direct transfer of data comes to an end. That is, the direct transfer of data comes to an end when the DMA request signal changes to the nonrequest level.
As will later be described, a conventional DMA request controlling arrangement comprises a sample-and-hold circuit. Supplied with the DMA request signal, the sample-and-hold circuit samples the DMA request signal into a sampled signal in synchronism with the sequence of clock pulses and holds the sampled signal as a held signal. Such sampling operation is carried out for the purpose of detecting the request and nonrequest levels of the DMA request signal.
Suppose that the peripheral device changes the DMA request signal for a first DMA request to the nonrequest level immediately after the peripheral device receives the DMA acknowledgement signal of the acknowledged level for the first DMA request in order to carry out the direct transfer of data, and that the peripheral device changes the DMA request signal for a second or different DMA request to the request level immediately after the DMA request signal changes to the nonrequest level for the first DMA request. More specifically, suppose that the peripheral device produces the second DMA request before the sample-and-hold circuit samples the DMA request signal of the nonrequest level for the first DMA request.
In this case, the sample-and-hold circuit determines that the peripheral device continuously produces the first DMA request although the peripheral device actually produces the second DMA request different from the first DMA request. This is because the sample-and-hold circuit samples the DMA request signal of the request level in response to a clock pulse without sampling the DMA request signal of the nonrequest level for the first DMA request. Thus, the conventional DMA request controlling arrangement malfunctions when the second DMA request is generated immediately after the peripheral device receives the DMA acknowledgement for the first DMA request.